FPGA SILICON
6 / 6 two-device hardware demos
Deterministic synchronization, identity, and integrity behaviors captured on real FPGA silicon across independent boards.
~2,828
GATE-EQUIVALENTS
DAD core, SKY130 sign-off · NIST-lightweight class · single-cycle updatealso ~580 LUT on Tang Primer 20K (FPGA, hardware-validated)
~0.64 mW
DYNAMIC @ 13.56 MHz
β4.7 mW at 100 MHz; 14.7 nW leakage · VCD-backannotated from post-route sign-off6 / 6
TWO-DEVICE FPGA DEMOS
deterministic sync, identity & integrity behaviors captured on real FPGA hardware · plus 5 DRC/LVS-clean GDSII layoutsDETERMINISTIC ARITHMETIC DYNAMICS
Drift is built on one deterministic arithmetic primitive: a compact, multiplier-free state recurrence that synthesizes to about 2,800 NIST-lightweight-class gate-equivalents.
We point it at a specific, honest problem β detecting transient faults and single-event upsets, and providing lightweight integrity and per-die identity, at a fraction of the area and power of redundancy-based approaches β for automotive and industrial functional safety and for radiation-prone (space) electronics.
WHAT'S PROVEN β THE EVIDENCE
Functional-correctness and engineering-feasibility results β not fabricated-silicon or security claims.
GDSII SIGN-OFF
5 DRC/LVS-clean GDSII layouts
Full place-and-route sign-off on the open-source SkyWater 130 nm PDK. EDA-characterized β not a fabricated chip.
MEASURED PPA
~2,828 GE Β· ~0.64 mW Β· 14.7 nW
From sign-off: ~2,828 gate-equivalents; β0.64 mW dynamic at 13.56 MHz (β4.7 mW at 100 MHz); 14.7 nW leakage.
LEAN 4
Machine-checked formal proofs
Lean proofs of the core's functional equivalence across configurations. View proof β
CAPABILITIES
SPACE / SAFETY
SEU detection without triple-modular redundancy
Single-event-upset detection via a monotone invariant of the computation, targeting a fraction of TMR's ~200% area overhead.
- Design-stage: coverage characterization and radiation beam-testing are on the roadmap.
INTEGRITY
Per-die identity & tamper-evidence
A lightweight screening / indication aid. Not cryptographic attestation.
BIST / TEST
Low-power BIST & deterministic test patterns
Built-in self-test and deterministic test-pattern (PRBS) generation. Passes standard statistical screens (NIST SP 800-22) β a statistical result, not a security claim.
ARCHITECTURE
Runtime-reconfigurable state width
A single datapath whose state width is selectable at runtime.
VALIDATED, NOT ASSERTED
Every figure on this page is measured β on real FPGA hardware, through full GDSII sign-off on an open PDK, and by machine-checked proof. This is functional and reliability hardware: fault and upset detection, lightweight integrity, and per-die identity, characterized at the design stage and ready to evaluate.
WHERE IT FITS
AUTOMOTIVE / INDUSTRIAL
Functional safety
Diagnostic-coverage / safety-mechanism IP under ISO 26262 / IEC 61508.
SPACE / DEFENSE
Radiation-tolerant electronics
Lightweight upset detection for COTS-based, SWaP-constrained systems.
MEDICAL DEVICE
Medical-device functional safety
Diagnostic-coverage for safety-critical electronics (IEC 60601 / 62304). Reliability / diagnostic coverage β not device security.
MATHEMATICAL FOUNDATIONS
Built on arithmetic dynamics over β€β, with machine-checked proofs of the implementation-safety properties (bounded carry, complete state coverage, temporal-extension equivalence).
S_next = Fold( (q*S + d) >> k )
FORMAL VERIFICATION
Machine-checked proofs of bounded carry and finite-state stability (Lean 4).
STATE COVERAGE
Provable state coverage via ErdΕs covering systems.
DRIFT-FLEX
Machine-checked temporal-extension equivalence (patent-pending).
GET INVOLVED
Collaborators: we're looking for a digital-design / verification engineer
(RTL, fault-injection) comfortable with the open-source silicon flow (OpenLane / SkyWater).
Evaluators & partners: get in touch below.